Renesas Electronics /R7FA6T2BD /GPT320 /GTBER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as GTBER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)BD0 0 (0)BD1 0 (0)BD2 0 (0)BD3 0 (0)DBRTECA 0 (0)DBRTECB 0 (00)CCRA 0 (Others)CCRB 0 (Others)PR0 (CCRSWT)CCRSWT 0 (00)ADTTA 0 (0)ADTDA 0 (00)ADTTB 0 (0)ADTDB

BD0=0, CCRA=00, ADTDB=0, PR=Others, CCRB=Others, ADTTB=00, ADTDA=0, ADTTA=00, DBRTECA=0, BD3=0, BD1=0, DBRTECB=0, BD2=0

Description

General PWM Timer Buffer Enable Register

Fields

BD0

GTCCR Buffer Operation Disable

0 (0): Buffer operation is enabled

1 (1): Buffer operation is disabled

BD1

GTPR Buffer Operation Disable

0 (0): Buffer operation is enabled

1 (1): Buffer operation is disabled

BD2

GTADTRA/GTADTRB Registers Buffer Operation Disable

0 (0): Buffer operation is enabled

1 (1): Buffer operation is disabled

BD3

GTDVU/GTDVD Registers Buffer Operation Disable

0 (0): Buffer operation is enabled

1 (1): Buffer operation is disabled

DBRTECA

GTCCRA Register Double Buffer Repeat Operation Enable

0 (0): GTCCRA register double buffer repeat operation is disabled

1 (1): GTCCRA register double buffer repeat operation is enabled

DBRTECB

GTCCRB Register Double Buffer Repeat Operation Enable

0 (0): GTCCRB register double buffer repeat operation is disabled

1 (1): GTCCRB register double buffer repeat operation is enabled

CCRA

GTCCRA Buffer Operation

0 (Others): Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD)

0 (00): No buffer operation

1 (01): Single buffer operation (GTCCRA <---->GTCCRC)

CCRB

GTCCRB Buffer Operation

0 (00): No buffer operation

0 (Others): Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF)

1 (01): Single buffer operation (GTCCRB <----> GTCCRE)

PR

GTPR Buffer Operation

0 (00): No buffer operation

0 (Others): Double buffer operation (GTPDBR --> GTPBR --> GTPR)

1 (01): Single buffer operation (GTPBR --> GTPR)

CCRSWT

GTCCRA and GTCCRB Forcible Buffer Operation

ADTTA

GTADTRA Register Buffer Transfer Timing Select

0 (00): In triangle wave or complementary PWM mode, no transfer. In saw-wave mode, no transfer.

1 (01): In triangle wave or complementary PWM mode, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.

2 (10): In triangle wave or complementary PWM mode, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.

3 (11): In triangle wave or complementary PWM mode, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.

ADTDA

GTADTRA Register Double Buffer Operation

0 (0): Single buffer operation (GTADTBRA --> GTADTRA)

1 (1): Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTRA)

ADTTB

GTADTRB Register Buffer Transfer Timing Select

0 (00): In triangle wave or complementary PWM mode, no transfer. In saw-wave mode, no transfer.

1 (01): In triangle wave or complementary PWM mode, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.

2 (10): In triangle wave or complementary PWM mode, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.

3 (11): In triangle wave or complementary PWM mode, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.

ADTDB

GTADTRB Register Double Buffer Operation

0 (0): Single buffer operation (GTADTBRB --> GTADTRB)

1 (1): Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTRB)

Links

() ()